The ambit in Fig 1 delivers 8A for active as abounding as two of today's high-performance, accelerated µPs. You can additionally optimize the architecture for lower accepted by alteration a few components. Most systems use a low-current 12V bent accumulation and a ailing adapted high-current 5V to ability the logic. However, the µP requires 3.3V for its capital ability voltage. Thus, an able dc/dc advocate that can catechumen 5 to 3.3V and accommodate a deeply adapted achievement voltage is necessary. The primary architecture objectives for this ambit were aspersing cost, eliminating the charge for calefaction sinks, and accouterment circumlocute aegis to aerate reliability.
A step-down (buck) regulator that operates at 80 kHz provides the 3.3V/8A output. IC1 drives the capital switching transistor, the N-channel Q3, through the Q1 and Q2 gate-drive transistors. Active drive for the aboideau of Q3 is all-important to aftermath actual fast switching transitions, which abbreviate switching losses.
The open-collector achievement of IC1's PWM dent controls Q1 and Q2. Back pin 6 pulls low, Q1 turns on through R9, and Q2 turns off, because D1 holds Q2's abject high. This activity pulls Q3's FET about-face up to 12V, which turns on Q3. Back pin 6 of IC1 is high, R7 turns on Q2, and R8 turns off Q1. In this state, the ambit pulls Q3's aboideau to ground, which turns it off. Q3, bolt diode D2, L1, C12, and C13 accommodate a dc achievement able of sourcing 8A of bulk current.
Note that you can use an 8A diode for D2 with alone a slight access in ability amusement in this device. Also, you can use a distinct 4700-µF achievement capacitor at the regulator achievement if achievement ripple and brief acknowledgment are not critical.
IC2, a attention advertence whose setpoint voltage is 3.3Vñ0.5%, provides acknowledgment and voltage control. Back the regulator achievement alcove 3.3V, IC2 sources accepted through R2 to ground, accouterment acknowledgment to the ascribe of IC1 and captivation the regulator achievement at 3.3V.
IC1 and faculty resistor R5 calmly apparatus overcurrent protection. Back the voltage bead beyond R5 exceeds 110 mV, IC1 activates its congenital pulse-by-pulse control, which banned the achievement current. R5 consists of a allotment of AWG 17 attrition wire (type MWS-294: MWS Industries, West Lake, CA, (818) 991-8553) with an able breadth of 1.5 in. You can additionally body R5 application the aforementioned breadth and barometer of manganin wire.
C16 charge sit actual abreast the cesspool of Q3, and C16's agnate alternation attrition (ESR) is critical. Do not acting a capacitor with college ESR. The aforementioned admonishing applies to C12 and C13 Booty affliction to analysis ESR specs if you use a substitute.
R1, R3, C3, and C6 set the bend advantage of IC1; C7 sets the oscillator frequency. C7 should be a acceptable affection bowl capacitor. C1, C2, C4, and C8 are all-important for ascribe bypassing, and they abate the bulk of switching babble the ambit conducts assimilate the ascribe lines. A snubber consisting of R10 and C10 is all-important to annihilate high-frequency campanology back Q3 switches off. These apparatus charge be amid as abutting as accessible to Q3. R13 and C17 accomplish the aforementioned action for D2.
Bench testing indicates the afterward ambit performance. For VIN5V, ability was 88% for a bulk accepted of 4A and 84% for a bulk accepted of 8.2A. For VIN5V and ILOAD8.2A, babble was 15-mV p-p and 5.5-mV rms application an HP34401A meter. The switcher backward in adjustment with no changes in the achievement voltage (1-mV altitude accuracy) back the bulk assorted from 0.1 to 8A and back the ascribe voltage assorted from 4.5 to 5.5V. With no calefaction sinks or airflow, the temperature of Q3 was 70øC and of D2 was 50øC, back operating at 8.2A connected bulk current.
All high-current switchers are acute to lath layout; booty affliction back designing the pc board. You'll access the best after-effects by application a multilayer board, so you can address a distinct band to arena plane. You should tie the "power" apparatus (C1, C2, C16, D2, C12, C13, C14) anon to this arena even and accumulation these apparatus so that the affiliation paths are as abbreviate as possible. You should affix the low-current ground, as Fig 1 shows, and again tie it to the ability arena at a distinct point abreast C13. Finally, all traces in the switching ability aisle (R5, Q3, and L1) charge be as abbreviate as possible. (DI #1688)
